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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* Fully integrated PLL * 9 LVCMOS/LVTTL outputs, 7 typical output impedance * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 15.625MHz to 250MHz * Input frequency range: 15.625MHz to 250MHz * VCO range: 250MHz to 500MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Cycle-to-cycle jitter: 36ps (typical) * Output skew: 125ps (maximum) * Static Phase Offset: TBD100ps (typical) * 3.3V supply voltage * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS/LVTTL Zero DeHiPerClockSTM lay Buffer and a member of the HiPerClockSTM family of High Performance Clocks Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The device is designed only for 1:1 input/output frequency ratios. The output divider allows a wide input/output frequency range with the 250MHz to 500MHz VCO. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be doubled by utilizing the ability of the outputs to drive two series terminated lines. The differential reference clock input will accept any differential signal levels.
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL VDDO VDDO GND GND Q6 Q8 Q7
Q0 SEL0 SEL1 Q1
32 31 30 29 28 27 26 25 VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FB_IN VDDO Q0 GND Q1 VDDO Q2 GND
24 23 22
Q2
/2 /4 /8 /16
VDDO Q5 GND Q4 VDDO Q3 GND MR/nOE
VDD CLK nCLK GND
Q3 Q4 Q5 Q6
0
CLK nCLK
PLL 1
ICS8602
21 20 19 18 17
DIV_SEL0 DIV_SEL1 GND
FB_IN PLL_SEL MR/nOE
Q7 Q8
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Type Power Power Input Input Power Input Input Power Output Pulldown Pullup Description Analog supply pin. Core supply pin. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. Feedback input to phase detector for regenerating clocks Pulldown with "zero delay". LVCMOS / LVTTL interface levels. Output supply pins. Clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and Pulldown the outputs are tri-stated (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. Pullup When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 8, 12 16, 18, 22, 25, 29 6, 7 9 10, 14, 20, 24, 27, 31 11, 13, 15, 19, 21, 23, 26, 28, 30 Name VDDA VDD CLK nCLK GND DIV_SEL0, DIV_SEL1 FB_IN VDDO Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8
17
MR/nOE
Input
32
PLL_SEL
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 51 VDD, VDDA, VDDO = 3.47V TBD 7 Test Conditions Minimum Typical Maximum 4 Units pF K K pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1
DIV_SEL1 0 0 1 1 DIV_SEL0 0 1 0 1 fOUT = fIN Frequency Range (MHz) Minimum Maximum 125 62.5 31.25 15.625 250 125 62.5 31.25
TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0 PLL BYPASS MODE
DIV_SEL1 0 0 1 1 DIV_SEL0 0 1 0 1 Frequency Divider fIN fIN fIN fIN fIN fOUT fIN/2 fIN/4 fIN/8 fIN/16
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 42.1C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 40 10 160 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current DIV_SEL0, DIV_SEL1, FB_IN, MR/nOE PLL_SEL DIV_SEL0, DIV_SEL1, FB_IN, MR/nOE PLL_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V
IIL VOH
Input Low Current
Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH IIL VPP VCMR Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum voltage for CLK, nCLK is VDD + 0.3V.
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions PLL_SEL=0V, 0MHz f 250MHz PLL_SEL = 3.3V, fREF = 133MHz, fVCO = 266MHz PLL_SEL = 3.3V, fREF = 50MHz, fVCO = 100MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 20% to 80% @ 50MHz 20% to 80% @ 50MHz 400 400 Minimum 15.625 TBD TBD100 TBD100 125 36 1 950 950 Typical Maximum 250 TBD Units MHz ns ps ps ps ps ms ps ps %
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tpLH Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Static Phase Offset; NOTE 2 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise Time Output Fall Time
t(O)
tsk(o) tjit(cc)
tL tR tF
odc Output Duty Cycle f = 250MHz 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDO = 1.65V5% VDD
SCOPE
nCLK
LVCMOS
Qx
CLK
V
PP
Cross Points
V
CMR
GND GND = -1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V Q0:Q8
DDO
V
DDO
V
DDO
V
Qx
DDO
2
n
2
2
2
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
V Q0:Q8 Pulse Width t
PERIOD DDO
odc =
t PW t PERIOD
odc & tPERIOD
nCLK CLK
FB_IN
t(O)
t(O) mean = Static Phase Offset
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET
8602BY
2
tcycle
tcycle n+1
V
Qy
DDO
2 tsk(o)
OUTPUT SKEW
80%
80%
20% Clock Outputs t
R
20% t
F
OUTPUT RISE/FALL TIME
nCLK CLK
VDD 2
Q0:Q8
VDDO 2 t
PD
PROPAGATION DELAY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8602 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F V DDA .01F 10 F 10
FIGURE 2. POWER SUPPLY FILTERING
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8602 is: 1828
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8602BY
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REV. F APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Marking ICS8602BY ICS8602BY Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8602BY ICS8602BYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8602BY
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REV. F APRIL 16, 2003

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